As a transistor ages over time and due to regular usage, the physical/electrical characteristics of the materials that make up the transistor may change. The changes in the physical/electrical characteristics of the materials may, for example, cause a switching speed of the transistor to become slower (more delayed) over time.
In current microprocessors, on-die monitors typically use a ring oscillator (RO) design to measure the impact of transistor aging on circuit delay. A feature of an RO design is the simple integration of the RO into existing product design flows because a RO is generally a self-contained circuit (e.g., a clock signal is not required). A problem with an RO design, however, is the severe underestimation of the impact of transistor aging on circuit delay.
With respect to a circuit path in a microprocessor, the worst-case delay degradation from transistor aging occurs when the path ages during a DC state, in which path nodes receive a constant DC voltage to keep specific transistor(s) in the path turned ON (such as a constant logic high level voltage to keep N-type transistors turned ON and/or a constant logic low level voltage to keep P-type transistors turned ON) and hence these transistor(s) are constantly under DC stress that contributes to the aging of the transistor(s). Such DC-stress during the DC state is the expected aging scenario for the vast majority of paths in a microprocessor. In general, increasing the level of DC voltage results in faster aging.
The path delay change due to DC stress depends significantly on the transition of the input signal being provided to the circuit path(s). Consider for example, a circuit path in which multiple pairs of N-type and P-type transistors are coupled in series, such that the first pair of transistors includes a N-type transistor and a P-type transistor, the second pair of transistors include another N-type transistor and another P-type transistor, and so forth. A single-transition input to the circuit path (such as an input binary signal going from logic high to logic low, or vice versa) will turn ON one of the transistors in the pair, while the other transistor in each pair is turned OFF.
The single-transition DC-stressed path delay that only propagates through stressed transistors represents the worst-case path delay degradation. In comparison, the opposite single-transition unstressed path delay that only propagates through non-stressed transistors may actually result in a delay improvement due to the reduced contention between stressed and non-stressed transistors in the path. In a conventional RO design, the RO's delay measurement averages the path delays from both transitions (e.g., stressed and unstressed path delays), thereby significantly underestimating the delay degradation.
Accordingly, even though a conventional RO design allows for simple integration into existing product design flows, the conventional RO design severely underestimates the impact of aging on circuit path delay since the path delays from both stressed and unstressed transitions are averaged. Hence, current on-die RO-based aging monitors are inadequate for measuring the effect of aging on path delays in a microprocessor or other circuitry.